The present invention relates to clock generators for generating a divide by 1.5 clock.
A divide by 1.5 clock generator is needed for providing the frequency of a clock used in a high speed READ channel for a disk drive. Typically a RLL (run-length limited) encoding clock is provided for clocking data off of a disk drive. In the READ channel, it is also necessary to have an NRZ (non-return to zero) clock with a frequency of 1/1.5=2/3 times the RLL clock. Typically, this is done in one of the following three manners.
First, a phase-locked loop frequency synthesizer can be used to generate the divide by 1.5 clock. Such a synthesizer can generate any division, not just a 1.5 division. The disadvantage of this approach is the requirement for a lot of circuitry, power, and silicon area.
A second approach is to multiply the RLL clock signal by 2, and then divide it by 3. Such a clock generator is believed to be used by Microlinear in its disk drive controller. The limitation of this sort of a system is that doubling the RLL clock is not possible when the RLL clock is near the fastest system clock available. Unless the system clock is at least twice as fast as the RLL clock, it is not possible to generate a doubled RLL clock.
A third approach, which is believed to be used by SGS Thompson, uses six dynamic latches in a shift register ring with a specific pattern which is cycled through the ring. This type of a circuit requires a power-on reset and also requires a pattern generation circuit, which in turn requires more effort in the debugging phase.
Another problem is that its output clock signal has a clock input to Q output delay compared to the input clock. This delay is hard to match and can cause racing problems.
A simpler, more reliable divide by 1.5 clock generator is desirable.